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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 143
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.20
7.20 Bcc:D (Branch relative if Condition satisfied)
This is a branching instruction with a delay slot. If the conditions established for each
particular instruction are satisfied, branch to the address indicated by label9 relative to
the value of the program counter (PC). When calculating the address, double the value
of rel8 as a signed extension. If conditions are not satisfied, no branching occurs.
● Assembler Format
BRA:D label9 BV:D label9
BNO:D label9 BNV:D label9
BEQ:D label9 BLT:D label9
BNE:D label9 BGE:D label9
BC:D label9 BLE:D label9
BNC:D label9 BGT:D label9
BN:D label9 BLS:D label9
BP:D label9 BHI:D label9
● Operation
if (condition) then
PC + 2 + exts(rel8 × 2) → PC
Branching conditions of each instruction are shown in Table 7.20-1.
Table 7.20-1 Branching conditions
Mnemonic cc Condition Mnemonic cc Condition
BRA:D 0000 Always satisfied BV:D 1000 V == 1
BNO:D 0001 Always unsatisfied BNV:D 1001 V == 0
BEQ:D 0010 Z == 1 BLT:D 1010 (V ^ N) == 1
BNE:D 0011 Z == 0 BGE:D 1011 (V ^ N) == 0
BC:D 0100 C == 1 BLE:D 1100 ((V ^ N) | Z) == 1
BNC:D 0101 C == 0 BGT:D 1101 ((V ^ N) | Z) == 0
BN:D 0110 N == 1 BLS:D 1110 (C | Z) == 1
BP:D 0111 N == 0 BHI:D 1111 (C | Z) == 0
| : Logical add (or) ^ : Exclusive-OR (exor) ==: comparison operation (satisfied by congruence)