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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 77
FR81 Family
CHAPTER 5 PIPELINE OPERATION
5.4
5.4 Non-block loading
Non-block loading is carried out in FR81 Family CPU. A maximum of 4 loading instructions
can be issued with precedence.
In non-block loading, the subsequent instruction is executed without waiting for the completion of loading
instruction, if the general-purpose register in which the load instruction value is stored is not referred in the
subsequent instruction.
As shown below, when register R1 that stores data value based on LD instruction is referred to in the
subsequent ADD instruction, the ADD instruction is executed after storing R1 value based on LD
instruction.
LD @10,R1
ADD R1,R2 ; waits for completion of execution of preceding LD instruction
As shown below, ADD instruction is executed without waiting for the completion of execution of LD
instruction when R1 that stores data value by LD instruction is not referred to in the subsequent ADD
instruction. After that, at the time of execution of SUB instruction that references R1, if the preceding LD
instruction is not already executed, the SUB instruction is executed after waiting for the completion of
execution of that LD instruction.
LD @10,R1
ADD R2,R3 ; Does not wait for completion of execution of preceding LD instruction
SUB R1,R3 ; waits for completion of execution of preceding LD instruction
A maximum of 4 load instructions can be executed with precedence. It can also be used in the following
way for issuing multiple LD instructions with precedence.
LD @100,R1 ; LD instruction (1)
LD @104,R2
LD @108,R3
LD @112,R4 ; a maximum of four LD instructions can be issued with precedence
ADD R5,R6 ; executed without waiting for the completion of execution of preceding LD
instruction
SUB R6,R0
ADD R1,R5 ; executed after completion of execution of preceding LD instruction (1)