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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 443
FR81 Family
APPENDIX
APPENDIX A Instruction Lists
Table A.2-14 Bit Search Instructions (3 Instructions)
Table A.2-15 Other Instructions (16 Instructions)
• In the ADD SP Instruction, the field s8 in TYPR-D Instruction Format has the following relation to the
value of s10 in assembly notation.
s8 = s10 >> 2
• In the ENTER Instruction, the field u8 in TYPR-D Instruction Format has the following relation to the
value of u10 in assembly notation.
u8 = u10 >> 2
Mnemonic
Format
OP CYC
FLAG
NZVC
RMW
Operation Remarks
Reference
SRCH0 Ri E 97-C 1 ---- - search_zero(Ri) → Ri Searches first 0 Bit 7.110
SRCH1 Ri E 97-D 1 ---- - search_one(Ri) → Ri Searches first 1 Bit 7.111
SRCHC Ri E 97-E 1 ---- - search_change(Ri) → Ri Searches first change 7.112
Mnemonic
Format
OP CYC
FLAG
NZVC
RMW
Operation Remarks
Reference
NOP E’ 9F-A 1 ---- -
No change
7.137
ANDCCR #u8 D 83 1 CCCC -
CCR & u8 → CCR
7.12
ORCCR #u8 D 93 1 CCCC -
CCR | u8 → CCR
7.141
STILM #u8 D 87 1 ---- -
u8 → ILM Sets ILM immediate value
7.126
ADDSP #s10 D A3 1 ---- -
R15+s8 × 4 → R15
7.8
EXTSB Ri E 97-8 1 ---- -
exts(Ri[7:0]) → Ri
Sign extension 8 → 32 7.59
EXTUB Ri E 97-9 1 ---- -
extu(Ri[7:0]) → Ri
Zero extension8 → 32 7.61
EXTSH Ri E 97-A 1 ---- -
exts(Ri[15:0]) → Ri
Sign extension 16 → 32 7.60
EXTUH Ri E 97-B 1 ---- -
extu(Ri[15:0]) → Ri
Zero extension16 → 32 7.62
LDM0 (reglist) D 8C *1 ---- -
for Ri of reglist
(R15) → Ri,
R15+4 → R15
Load Multiple
R0 to R7
7.109
LDM1 (reglist) D 8D *1 ---- -
for Ri of reglist
(R15) → Ri,
R15+4 → R15
Load Multiple
R8 to R15
7.110
STM0 (reglist) D 8E *2 ---- -
for Ri of reglist
R15-4 → R15,
Ri → (R15)
Store multiple
R0 to R7
7.127
STM1 (reglist) D 8F *2 ---- -
for Ri of reglist
R15-4 → R15,
Ri → (R15)
Store multiple
R8 to R15
7.128
ENTER #u10 D 0F 1+a ---- -
R14 → (R15-4) ,
R15-4 → R14,
R15-extu(u8 × 4) → R15
Function entry
processing
7.54
LEAVE E’ 9F-9 b ---- -
R14+4 → R15,
(R15-4) → R14
Function exit processing 7.85
XCHB @Rj, Ri A 8A 2a ---- ❍
Ri → TEMP,
extu((Rj)) → Ri,
TEMP → (Rj)
Byte data for semaphore
processing
7.132
*1: The number of execution cycles for LDM0(reglist) and LDM1(reglist) is b × n cycles when "n" is the number of
registers designated.
*2: The number of execution cycles for STM0(reglist)and STM1(reglist) is a × n when "n" is the number of registers
designated.