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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 79
FR81 Family
CHAPTER 5 PIPELINE OPERATION
5.5
Figure 5.5-2 Example of processing of Non-Delayed Branching instruction
(Branching conditions not satisfied)
5.5.2 Example of processing of delayed branching instruction
Delayed branching instructions are processed with an apparent execution speed of 1 cycle, regardless of
whether or not branching conditions are satisfied. When branching occurs, this is one cycle faster than
using non-delayed branching instructions. However, the apparent order of instruction processing is inverted
in cases where branching occurs.
An instruction immediately following a branching instruction will already be loaded by the CPU by the
time the branching instruction is executed. This position is called the delay slot. A delayed branching
instruction is a branching instruction that executes the instruction in the delay slot regardless of whether or
not branching conditions are satisfied.
Figure 5.5-3 shows an example of processing a delayed branching instruction when branching conditions
are satisfied. In this example, the branch destination instruction "ST R2,@R13" is executed after the
instruction "ST R2,@R12" in the delay slot. As a result, the branching instruction has an apparent
execution speed of 1 cycle. However, the instruction "ST R2,@R12" in the delay slot is executed before
the branch destination instruction "ST R2,@R13" and therefore the apparent order of processing is
inverted.
Figure 5.5-3 Example of processing of Delayed Branching instruction (Branching conditions satisfied)
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
Not canceled
IF ID EX MA WB
LD @R10, R1
LD @R11, R2
ADD R1, R3
ST R2, @R12(instruction immediately after)
ADD #4, R12(subsequent instruction)
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
Not canceled
IF ID EX MA WB
LD @R10, R1
LD @R11, R2
ADD R1, R3
ST R2, @R12(delay slot instruction)
ST R2, @R13(branch destination instruction)
: PC change