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FR81 Family
2 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
1.1
1.1 Features of FR81 Family CPU
FR81 Family CPU is meant for 32 bit RISC controller having proprietary FR81
architecture of Fujitsu. The FR81 architecture is optimized for microcontrollers by using
the FR family instruction set and including improved floating-point, memory protection,
and debug functions.
■ General-purpose Register Architecture
It is load/store architecture based on 16 numbers of 32-bit General-purpose registers R0 to R15. The
architecture also has instructions that are suitable for embedded uses such as memory to memory transfer,
bit processing etc.
■ Linear Space for 32-bit (4G bytes) addressing
Address space is controlled for each byte unit. Linear specification of Address is made based on 32-bit
address.
■ 16-bit fixed instruction length (excluding immediate data transfer instructions)
It is 16-bit fixed length instruction format excluding 32/20-bit immediate data transfer instruction. It
enables securing high object efficiency.
■ Floating point calculation unit (FPU)
FR81 Family supports single precision floating point calculation (IEEE754 compliant). It has 16 pieces of
32-bit floating point registers from FR0 to FR15. A single instruction can execute a product-sum operation
type calculation (multiplication, or addition/subtraction). The instruction length of a floating point type
instruction is 32 bits
■ Pipeline Configuration
High speed one-instruction one-cycle processing of the basic instructions based on 5-stage pipeline
operation can be carried out. Pipeline has following 5-stage configuration.
• IF Stage: Load Instruction
• ID Stage: Interpret Instruction
• EX Stage: Execute Instruction
• MA Stage: Memory Access
• WB Stage: Write to register
FR81 Family has the 6-stage pipeline configuration to execute floating point type instructions.
■ Non-blocking load
In FR81 Family, non-blocking loading is carried out making execution of LD (load) instructions efficient.
A maximum of four LD (Load) instructions can be issued in anticipation. In non-blocking, succeeding
instruction is executed without waiting for the completion of a load instruction, in case general-purpose
register storing the value of load instruction is not referred by the succeeding instruction.