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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 165
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.31
7.31 CMP (Compare Immediate Data and Destination Register)
Subtracts the result of the higher 28 bits of 4-bit immediate data with zero extension
from the word data in Ri, sets results in the flag of condition code register (CCR).
● Assembler Format
CMP #i4, Ri
● Operation
Ri - extu(i4)
● Flag Change
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Classification
Compare instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
NZVC
CCCC
MSB LSB
10101000 i4 Ri