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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 55
FR81 Family
CHAPTER 4 RESET AND "EIT" PROCESSING
4.5
4.5.2 Non-maskable Interrupts (NMI)
Non-maskable interrupts (NMI) are interrupts that cannot be masked.
Depending upon the product series, there are models which do not support NMI (there are no external NMI
terminals). Refer to the hardware manual of various models to check whether NMI is supported or not.
Even if the acceptance of interrupts have been restricted by setting of "0" in the interrupt enable flag (I) of
the condition code register (CCR), interrupts generated by NMI cannot be restricted. The masking of
interrupt level by the interrupt level mask register (ILM) is valid. If a value above 16(10000
B
) is set in the
interrupt level mask register (ILM) by a program, normally "NMI" cannot be masked by the interrupt level.
The value of interrupt level mask register (ILM) is initialized to 15(01111
B
) following a reset. Therefore,
NMI cannot be masked until a value above 16(10000
B
) by a program following a reset.
When an NMI is accepted, the following operations are performed.
1. Transition to privilege mode is carried out, the stack flag (S) is cleared, and 15 is set to the interrupt
level mask register (ILM).
"0" → UM "0" → S "15" → ILM
2. The contents of the program status (PS) are saved to the system stack
SSP - 4 → SSP PS →(SSP)
3. The address of the instruction next to that accepted NMI is saved to the system stack.
SSP - 4 → SSP next instruction address → (SSP)
4. The program counter (PC) value is updated by referring to the vector table.
(TBR + 3C0
H
) → PC
5. A new EIT event is detected.
4.5.3 Break Interrupt
A break interrupt is used for break request from the debugger. The break interrupt is reported by a level,
and accepted when the level is higher than that of the interrupt level mask register (ILM). The request
levels from 0 to 31 are available. The level cannot be masked by the interrupt enable flag (I).
The following describes conditions to accept the break interrupt. When the conditions are met, the CPU
accepts the break interrupt.
• When a break interrupt request level is higher than that of the interrupt level mask register (ILM)
• When the CPU is operating in the user state during debugging
The following describes the brake processing being carried out when the break interrupt is accepted.
1. Transition to privilege mode is carried out, the stack flag (S) cleared, 4 is set to the interrupt level mask
register (ILM), and then the mode is shifted to the debug state.
"0" → UM "0" → S "4" → ILM
2. The code event is determined for the instruction next to that accepted the break interrupt.