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FR81 Family
74 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 5 PIPELINE OPERATION
5.3
5.3 Pipeline hazards
The FR81 Family CPU executes program steps in the order in which they are written and
is therefore equipped with a function that detects the occurrence of data hazards and
construction hazards, and stops pipeline processing when necessary.
5.3.1 Occurrence of data hazard
A data hazard occurs if dependency that refers or updates the register exists in between the preceding and
subsequent instructions. The CPU may simultaneously process one instruction that involves writing values
to a register, and a subsequent instruction that attempts to refer to the same register before the write process
is completed.
An example of a data hazard is shown in Figure 5.3-1. In this case, the reading of R1 used as the address
will read the value before the modification, as the read timing precedes the writing to R1 requested by the
just previous instruction. (Actually, the data hazard is avoided, and the modified value is read.)
Figure 5.3-1 Example of a data hazard
5.3.2 Register Bypassing
Even when a data hazard does occur, it is possible to process instructions without operating delays if the
data intended for the register to be accessed can be extricated from the preceding instruction. This type of
data transfer processing is called register bypassing.
An example of Register Bypassing is indicated in Figure 5.3-2. In this example, instead of reading the R1
in the ID stage of SUB instruction, the program uses the results of the calculation from ADD instruction
(before the results are written to the register) and thus executes the instruction without delay.
Figure 5.3-2 Example of a register bypass
IF ID EX MA WB : Write cycle to R1
: Read cycle from R1
IF ID EX MA WBSUB R1, R2
ADD R0, R1
IF ID EX MA WB : Data calculation cycle to R1
: Read cycle from R1
IF ID EX MA WBSUB R1, R2
ADD R0, R1