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80 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 5 PIPELINE OPERATION
5.5
Figure 5.5-4 shows an example of processing a delayed branching instruction when branching conditions
are not satisfied. In this example, the instruction "ST R2,@R12" in delay slot is executed without being
cancelled. As a result, the program is processed in the order in which it is written. The branching
instruction requires an apparent processing time of 1 cycle.
Figure 5.5-4 Example of processing of Delayed Branching instruction
(Branching conditions not satisfied)
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
LD @R10, R1
LD @R11, R2
ADD R1, R3
BNE:D TestOK (br
ST R2, @R12 (delay slot instruction)
ADD #4, R12
Not canceled