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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 57
FR81 Family
CHAPTER 4 RESET AND "EIT" PROCESSING
4.6
4.6 Traps
Traps are generated from within the instruction sequence. Traps are processed by first
saving the necessary information to resume processing from the next instruction in the
sequence, and then starting the processing routine corresponding to the type of the
trap that has occurred.
Branching to the processing routine takes place after execution of the instruction that has caused the trap.
The address of the instruction in which the trap occurs becomes the program counter (PC) value that is
saved to the stack at the time of trap generation.
Following factors can lead to generation of traps.
•INT instruction
• INTE instruction
• Step trace traps
4.6.1 INT Instructions
The "INT #u8" instruction is used to create a trap through software. It generates a trap corresponding to the
interrupt number designated in the operand.
When the INT instruction is executed, the following operations take place.
1. Transition to privilege mode is carried out, and the stack flag (S) is cleared.
"0" → UM "0" → S
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP PS → (SSP)
3. The address of the next instruction is saved to the system stack.
SSP - 4 → SSP next instruction address → (SSP)
4. The program counter (PC) value is updated by referring to the vector table.
(TBR + 3FC
H
- 4 × u8) → PC
5. A new EIT event is detected.
The value of program counter (PC) saved to the system stack represents the address of the next instruction
after the INT instruction.
4.6.2 INTE Instruction
The INTE instruction is used to create a software trap for debugging. A trap does not occur when the
system is in the debug state during debugging, or if the step trace trap flag (SCR:T) of the program status
(PS) is set. The operation of the INTE instruction varies between the user state during debugging and
normal operation.