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FR81 Family
100 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 6 INSTRUCTION OVERVIEW
6.6
6.6 Step Division Instructions
In FR81 Family CPU, 32-bit signed/unsigned division is carried out based on combination
of Step Division Instructions.
Step Division Instructions are of following types.
• DIV0S (Initial Setting Up for Signed Division)
• DIV0U (Initial Setting Up for Unsigned Division)
• DIV1 (Main Process of Division)
• DIV2 (Correction When Remain is zero)
• DIV3 (Correction When Remain is zero)
• DIV4S (Correction Answer for Signed Division)
In order to realize signed division, combine the Instructions as follows.
DIV0S, DIV1 × 32, DIV2, DIV3, DIV4S
In order to realize unsigned division, combine the Instructions as follows.
DIV0U, DIV1 × 32
For various Instructions, see "CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS".
6.6.1 Signed Division
Signed 32bit dividend is divided with signed 32 bit divisor and quotient of signed 32 bit and remainder of
signed 32bit are obtained.
Before carrying out division, dividend and divisor are set in the following register.
• Multiplication/Division Register (MDL): Dividend of signed 32 bit (Dividend)
• One of general-purpose registers: Divisor of signed 32 bit (Divisor)
Signed division is carried out by executing following 36 Instructions. DIV1 Instructions 32 numbers are
arranged after DIV0S Instructions. In the operand of DIV0S Instructions, DIV1 Instructions, DIV2
Instructions general-purpose registers that store divisor are specified.
DIV0S R2 ; Divisor in R2
DIV1 R2 ; #1
DIV1 R2 ; #2
. . .
DIV1 R2 ; #30