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304 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.110
7.110 LDM1 (Load Multiple Registers)
Loads the word data of address R15 to multiple registers R8 to R15 specified in reglist,
repeats the operation of adding 4 to R15. Registers are processed in ascending
numerical order. If R15 is specified in the parameter reglist, the final contents of R15
will be read from memory.
● Assembler Format
LDM1 (reglist)
Registers from R8 to R15 are separated in reglist, multiple register are arranged and specified.
● Operation
The following operations are repeated according to the number of registers specified in the parameter
reglist.
(R15) → Ri
R15+4 → R15
Bit values and register numbers for reglist (LDM1) are shown in Table 7.110-1.
Table 7.110-1 Bit values and register numbers for reglist (LDM1)
● Flag Change
N, Z, V, C: Unchanged.
Bit Register
7R15
6R14
5R13
4R12
3R11
2R10
1R9
0R8
NZVC
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