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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 101
FR81 Family
CHAPTER 6 INSTRUCTION OVERVIEW
6.6
DIV1 R2 ; #31
DIV1 R2 ; #32
DIV2 R2
DIV3
DIV4S
Division results are stored in the following registers.
• Multiplication/Division Register (MDL): quotient of signed 32 bit
• Multiplication/Division Register (MDH): remainder of signed 32 bit
Example of execution of signed division has been indicated in Figure 6.6-1.
Figure 6.6-1 Example of execution of signed division
In SOFTUNE Assembler, DIV Instruction has been arranged to carry out signed division as Assembler
Pseudo Machine Instruction. Using this DIV Instruction in place of above mentioned 36 Instructions,
signed division can be described with 1 Instruction. See "FR family SOFTUNE Assembler Manual" for
DIV Instruction.
6.6.2 Unsigned Division
Dividend of unsigned 32 bit dividend is divided with unsigned 32bit divisor and quotient of unsigned 32 bit
and remainder of unsigned 32 bit are obtained.
Before carrying out division, dividend and divisor are set in the following register.
• Multiplication/Division Register (MDL): Dividend of unsigned 32 bit (Dividend)
• One of general-purpose registers: Divisor of unsigned 32 bit (Divisor)
Unsigned division is carried out by executing following 33 Instructions. DIV1 Instructions 32 numbers are
arranged after DIV0U Instruction. In the operand of DIV0U Instructions, DIV1 Instructions, general-
purpose registers that store divisor are specified.
MDH
MDL
D1 D0 T
SCR SCR
××0
D1 D0 T
110
R2
MDH
MDL
R2
FFFFFFFF
FEDCBA98
××××××××
0123 4567
Before execution After execution
FFFFFFFF
0123 4567