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FR81 Family
238 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.68
7.68 FDIVs (Single Precision Floating Point Division)
FRk is divided by FRj, and its result is stored in FRi.
● Assembler Format
FDIVs FRk, FRj, FRi
● Operation
FRk / FRj → FRi
● Classification
Single-precision floating point instruction, FR81 family
● Execution Cycles
9 cycles
● Instruction Format
● EIT Occurrence and Detection
An invalid instruction exception (FPU absence error), an FPU exception, or an interrupt is detected.
MSB LSB
(n+0)0000011110101010
(n+2) - FRk FRj FRi