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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 3
FR81 Family
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
1.1
■ Harvard Architecture
An instruction can be executed efficiently based on Harvard Architecture where instruction bus for
instruction access and data bus for data access are independent.
■ Multiplication Instruction
Multiplication/division computation can be executed at the instruction level based on an in-built multiplier.
32-bit multiplication, signed or unsigned, is executed in 5 cycles. 16-bit multiplication is executed in 3
cycles.
■ Step Division Instruction
32-bit ÷ 32-bit division, signed or unsigned, can be executed based on combination of step division
instructions.
■ Direct Addressing Instruction for peripheral access
Address of 256 words/ 256 half-words/ 256 bytes from the top of address space (low order address) can be
directly specified. It is convenient for address specification in the I/O Register of the peripheral resource.
■ High-speed interrupt processing complete within 6 cycles
Acceptance of interruption is processed at a high speed within 6 cycles. A 16-level priority order is given to
the request for interruption. Masking in line with the priority order can be carried out based on interruption
mask level of the CPU.