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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 447
FR81 Family
APPENDIX
APPENDIX A Instruction Lists
Table A.2-21 FPU Branching Instruction with Delay (16 Instructions)
• Delayed Branching Instructions are branched after always executing the following Instruction (the Delay
Slot).
• The field rel16 in TYPE-N instruction format has the following relation to the value label17 in assembly
notation.
rel16 = (label17-PC-4)/2
Mnemonic
Format
OP CYC
FCC
ELGU
RMW
Operation Remarks
Reference
FBN:D N 17-F0 2 ---- - No branch 7.66
FBA:D label17 N 17-FF 2 ---- -
PC+4+exts(rel16 × 2) → PC
7.66
FBNE:D label17 N 17-F7 2 ---- -
if ( L || G || U ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBE:D label17 N 17-F8 2 ---- -
if ( E ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBLG:D label17 N 17-F6 2 ---- -
if ( L || G ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBUE:D label17 N 17-F9 2 ---- -
if ( E || U ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBUL:D label17 N 17-F5 2 ---- -
if ( L || U ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBGE:D label17 N 17-FA 2 ---- -
if ( G || E ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBL:D label17 N 17-F4 2 ---- -
if ( L ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBUGE:D label17 N 17-FB 2 ---- -
if ( U || G || E ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBUG:D label17 N 17-F3 2 ---- -
if ( U || G ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBLE:D label17 N 17-FC 2 ---- -
if ( L || E ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBG:D label17 N 17-F2 2 ---- -
if ( G ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBULE:D label17 N 17-FD 2 ---- -
if ( E || L || U ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBU:D label17 N 17-F1 2 ---- -
if ( U ) then
PC+4+exts(rel16 × 2) → PC
7.66
FBO:D label17 N 17-FE 2 ---- -
if ( E || L || G ) then
PC+4+exts(rel16 × 2) → PC
7.66