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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 67
FR81 Family
CHAPTER 4 RESET AND "EIT" PROCESSING
4.10
4.10 Precautions
The precautions of The reset and the EIT processing described here.
4.10.1 Exceptions in EIT Sequence and RETI Sequence
If a data access protection violation exception (including guarded access break) or invalid instruction
exception (data access error) occurs in the EIT or RETI sequence, since access to the system stack area is
disabled, the CPU goes into the inactive state. To restore the system from this state, reset the system or
execute a break interrupt from the debugger.
At this time, the data access protection violation exception or invalid instruction exception (data access
error) cannot be accepted, and the processing is stopped immediately. The reset process/break process starts
when a reset or break request is detected in the CPU stopped. If the CPU shifts to this stop state, since the
EIT or RETI sequence is stopped in the middle of execution, it is impossible to execute the user program
with this condition.
4.10.2 Exceptions in Multiple Load and Multiple Store
Instructions
If a data access protection violation exception, invalid instruction exception (data access error), or guarded
access break (data access) occurs when the LDM0, LDM1, STM0, STM1, FLDM or FSTM instruction is
executed, the result of the processing up to this point is reflected in the memory or R15 (SSP/USP). The list
of registers that have not been executed is stored in the register list of the exception status register (ESR).
4.10.3 Exceptions in Direct Address Transfer Instruction
If a data access protection violation exception, invalid instruction exception (data access error), or guarded
access break (data access) occurs when data is transferred from the direct area to the memory by the direct
address transfer instruction (DMOV), the I/O register value is updated when the I/O register value in the
direct area is changed by reading.