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50 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 4 RESET AND "EIT" PROCESSING
4.4
If this exception occurs while executing LDM0, LDM1, STM0, STM1, FLDM, or FSTM instruction,
contents of execution until the occurrence are reflected in registers and memory. Check the register list
(ESR:RL) for how far the instruction is executed.
Upon acceptance of the instruction access protection violation exception, the following operations take
place.
1. Transition to privilege mode is carried out, and the stack flag (S) is cleared.
"0" → UM "0" → S
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP PS → (SSP)
3. The contents of the program counter (PC) of an exception source instruction are saved to the system
stack.
SSP - 4 → SSP PC → (SSP)
4. The program counter (PC) value is updated by referring to the vector table.
(TBR + 3E0
H
) → PC
5. A new EIT event is detected.
4.4.4 FPU Exception
An FPU exception occurs when a floating point instruction is executed. The occurrence of the floating
point exception can be restrained with the floating point control register (FCR).
To prevent a subsequent instruction from being completed before detection of the FPU exception, when the
FPU exception is enabled, a pipeline hazard should be generated in order to stall the pipeline. Thus the
subsequent instruction will not pass the floating point instruction.
The following describes sources causing the FPU exception. For details on conditions of the occurrence,
see the description of each instruction.
• When an unnormalized number has been input while the unnormalized number input is enabled.
• When the calculation result has become inexact while the inexact exception is enabled.
• When an underflow has occurred in the calculation result while the underflow exception is enabled.
• When an overflow has occurred in the calculation result while the overflow exception is enabled.
• When a division-by-zero operation has occurred while the division-by-zero exception is enabled.
• When an invalid calculation has been executed while the invalid calculation exception is enabled.
Upon acceptance of the FPU exception, the following operations take place.
1. Transition to privilege mode is carried out, and the stack flag (S) is cleared.
"0" → UM "0" → S
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP PS → (SSP)