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7.155 ST (Store Word Data in Register to Memory) ................................................................................. 390
7.156 ST (Store Word Data in Program Status Register to Memory) ....................................................... 392
7.157 STB (Store Byte Data in Register to Memory) ................................................................................ 394
7.158 STB (Store Byte Data in Register to Memory) ................................................................................ 396
7.159 STB (Store Byte Data in Register to Memory) ................................................................................ 398
7.160 STB (Store Byte Data in Register to Memory) ................................................................................ 400
7.161 STH (Store Halfword Data in Register to Memory) ......................................................................... 401
7.162 STH (Store Halfword Data in Register to Memory) ......................................................................... 403
7.163 STH (Store Halfword Data in Register to Memory) ......................................................................... 405
7.164 STH (Store Halfword Data in Register to Memory) ......................................................................... 407
7.165 STILM (Set Immediate Data to Interrupt Level Mask Register) ...................................................... 408
7.166 STM0 (Store Multiple Registers) ..................................................................................................... 410
7.167 STM1 (Store Multiple Registers) ..................................................................................................... 412
7.168 SUB (Subtract Word Data in Source Register from Destination Register) ..................................... 414
7.169 SUBC (Subtract Word Data in Source Register and Carry bit from Destination Register) ............. 416
7.170 SUBN (Subtract Word Data in Source Register from Destination Register) ................................... 418
7.171 XCHB (Exchange Byte Data) .......................................................................................................... 420
APPENDIX ......................................................................................................................... 423
APPENDIX A Instruction Lists ............................................................................................................ 424
A.1 Meaning of Symbols ....................................................................................................................... 425
A.1.1 Mnemonic and Operation Columns ....................................................................................... 425
A.1.2 Operation Column ................................................................................................................. 430
A.1.3 Format Column ...................................................................................................................... 431
A.1.4 OP Column ............................................................................................................................ 431
A.1.5 CYC Column .......................................................................................................................... 432
A.1.6 FLAG Column ........................................................................................................................ 433
A.1.7 RMW Column ........................................................................................................................ 433
A.1.8 Reference Column ................................................................................................................. 433
A.2 Instruction Lists .............................................................................................................................. 434
A.3 List of Instructions that can be positioned in the Delay Slot ........................................................... 448
APPENDIX B Instruction Maps ........................................................................................................... 450
B.1 Instruction Maps ............................................................................................................................. 451
B.2 Extension Instruction Maps ............................................................................................................ 452
APPENDIX C Supplemental Explanation about FPU Exception Processing ...................................... 455
C.1 Conformity with IEEE754-1985 Standard ...................................................................................... 455
C.2 FPU Exceptions ............................................................................................................................. 456
C.3 Round Processing .......................................................................................................................... 458
INDEX................................................................................................................................... 461