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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 121
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.9
7.9 AND (And Word Data of Source Register to Data in
Memory)
Takes the logical AND of the word data at memory address Ri and word data in Rj and
stores the results to the memory address corresponding to Ri.
● Assembler Format
AND Rj,@Ri
● Operation
(Ri) & Rj → (Ri)
● Flag Change
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is zero, cleared otherwise.
V, C: Unchanged.
● Classification
Logical calculation instruction, Read/Modify/Write type instruction
● Execution Cycle
1+2a cycles
● Instruction Format
NZV C
CC - -
MSB LSB
10000100 Rj Ri