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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 23
CHAPTER 3 PROGRAMMING MODEL
3.3
3.3.6 Condition Code Register (CCR)
Condition code register (CCR) is an 8-bit register that indicates the status of instruction execution. It lies
between bit7 to bit0 of the program status (PS).
Figure 3.3-7 shows the bit configuration of condition code register (CCR).
Figure 3.3-7 Condition Code Register (CCR) Bit Configuration
The contents of each bit are described below.
[bit7, bit6] Reserved
These are reserved bits. Read value is always "0". Write value should always be "0".
[bit5] S: Stack Flag
This flag selects the stack pointer to be used as general-purpose register R15. When the value of
stack flag (S) is "0", system stack pointer (SSP) is used, while when the value is "1", user stack
pointer (USP) is used.
Table 3.3-3 Stack Flag (S) of Condition Code Register
If an EIT operation is accepted, stack flag (S) automatically becomes "0". However, the value of the
condition code register (CCR) saved in system stack is the value which is later replaced by "0".
The initial value of stack flag (S) after a reset is "0".
[bit4] I: Interrupt Enable Flag
This flag is used to enable/disable mask-able interrupts. The value "0" of interrupt enable flag (I)
disables an interrupt while "1" enables an interrupt. When an interrupt is enabled, the mask
operation of interrupt request is performed by interrupt level mask register (ILM).
Table 3.3-4 Interrupt Enable Flag (I) of Condition Code Register
The value of this flag is replaced by "0" by execution of INT instruction. However, the value of
condition code register (CCR) saved in the system stack is the value which is later replaced by "0".
The initial value of an interrupt enable flag (I) after a reset is "0".
CCR ReservedReserved
S INZVC
bit7 bit6 bit5 bit4 bit3bit2 bit1 bit0
Initial value
--00XXXX
B
flag value Meaning
S
0 System stack pointer (SSP)
1 User stack pointer (USP)
flag Value Meaning
I
0 Interrupt disable
1 Interrupt enable