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36 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 3 PROGRAMMING MODEL
3.3
■ Floating point exception flag (CFE)
Floating point exception flag (CFE) is a 6-bit register that indicates the exception occurrence of floating
point calculation. It lies between bit 5 and bit 0 of the FPU control register (FCR). Each flag is set
according to the calculation result. Each flag shall be cleared using software. Each flag can be set only to
"0", and writing "1" to the flag is invalid. The write value is evaluated by bit. If the flag has not been
cleared during exception processing, each flag is cumulated.
Figure 3.3-27 shows the bit configuration of the floating point exception flag (CFE).
Figure 3.3-27 Floating point exception flag (CFE) Bit Configuration
The content of each bit are described below.
[bit5] D : D flag
This flag is set when an unnormalized number has been input while the unnormalized number input
exception is enabled (EEF:D=1).
[bit4] X : X flag
This flag is set when the calculation result has become inexact while the inexact exception is
enabled (EEF:X=1).
[bit3] U : U flag
This flag is set when an underflow has occurred in the calculation result while the underflow
exception is enabled (EEF:U=1).
[bit2] O : O flag
This flag is set when an overflow has occurred in the calculation result while the overflow exception
is enabled (EEF:O=1).
[bit1] Z : Z flag
This flag is set when a division by zero has occurred while the division-by-zero exception is enabled
(EEF:Z=1).
[bit0] V : V flag
This flag is set when an invalid calculation has been carried out while the invalid calculation
exception is enabled (EEF:V=1).
bit3bit2bit5 bit4 bit1 bit0
UXDOZV
Initial value
XXXXXX
B