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FR81 Family
4 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
1.2
1.2 Changes from the earlier FR Family
FR81 Family has partial addition and deletion of instructions and operational changes
from the earlier FR Family (FR30 Family, FR60 Family etc.).
■ Instructions that cannot be used in FR81/FR80 Family
Following instructions cannot be used in FR81/FR80 Family.
• Coprocessor Instructions (COPOP, COPLD, COPST, COPSV)
• Resource Instructions (LDRES, STRES)
Undefined Instruction Exceptions and not the Coprocessor Error Trap occur when execution of
Coprocessor Instruction is attempted. Undefined Instruction Exceptions occur when execution of Resource
Instruction is attempted.
■ Instructions added to FR81/FR80 Family
Following instructions have been added in FR81/FR80 Family. These instructions have replaced the bit
search module embedded as a peripheral function.
• SRCH1 (Bit Search Instruction Detection of First "1" bit from MSB to LSB)
• SRCH0 (Bit Search Instruction Detection of first "0" bit from MSB to LSB)
• SRCHC (Bit Search Instruction Detection of Change point from MSB to LSB)
see "Chapter 7 Detailed Execution Instructions" and "Appendix A 2 Instruction Lists" for operation of Bit
Search Instructions.
■ Adding floating point type instructions
Floating point type instructions and 16 pieces of 32-bit floating point registers (FR0 to FR15) have been
added in FR81 Family.
■ Privilege mode
Privilege mode has been added in FR81 family. Privilege mode and user mode are two CPU operation
modes.
■ Exception processing
Exception processing has been improved for FR81 Family. The following exceptions have been added.
• FPU exception
• Instruction access protection violation exception
• Data access protection violation exception
• Invalid instruction exception (Changing definition from undefined instruction exception)
• Data access error exception
• FPU absence exception