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FR81 Family
76 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 5 PIPELINE OPERATION
5.3
5.3.6 Control Hazard
A control hazard occurs when the next instruction cannot be fetched before the branching instruction is
complete. In FR81 Family, to reduce penalty due to this control hazard, the pre-fetch function that bypasses
the branch destination address from the ID stage and the delayed branching instruction have been added.
Therefore, penalties do not become apparent.
● Pre-fetch function
FR81 Family CPU has a 32-bit 4-stage pre-fetch buffer, and fetches a subsequent instruction of consecutive
addresses as long as the buffer is not full. However, when a branching instruction is decoded, the
instruction is fetched from the branching destination regardless of the condition. If an instruction is
branched, the instruction in the pre-fetch buffer is discarded, and the subsequent instruction in the
branching destination will be pre-fetched. If not branched, the instruction in the branching destination is
discarded, and the instruction in the pre-fetch buffer will be used.
● Delayed branching processing
Delayed branching processing is the function to execute the instruction immediately following the
branching instruction for pipeline operation by one, regardless of whether the branching is successful or
unsuccessful. The position immediately following a branching instruction is called the delay slot.
Instructions that can be placed in the delay slot should be executable in one state having 16-bit length.
Placing an instruction that does not fit in the delay slot will result an invalid instruction exception to occur.
Refer to Appendix A.3 for the list of instructions that can be placed in delay slot.