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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 257
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.81
7.81 FNEGs (Single Precision Floating Point sign reverse)
A sign of FRj value is inverted, and the result is stored in FRi.
● Assembler Format
FNEGs FRj, FRi
● Operation
FRj × -1 → FRi
● Classification
Single-precision floating point instruction, FR81 family
● Execution Cycles
1 cycle
● Instruction Format
● EIT Occurrence and Detection
An invalid instruction exception (FPU absence error), an interrupt is detected.
MSB LSB
(n+0)0000011110101111
(n+2) - - FRj FRi