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38 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 3 PROGRAMMING MODEL
3.3
■ Invalid instruction exception source (INV)
Invalid instruction exception source (INV) is a 7-bit register that indicates the source causing an invalid
instruction exception. It lies between bit 6 and bit 0 of the exception status register (ESR). Each flag is set
only when the source occurs. Each flag shall be cleared using software. Each flag can be set only to "0",
and writing "1" to the flag is invalid. The write value is evaluated by bit.
Figure 3.3-30 shows the bit configuration of the invalid instruction exception source (INV).
Figure 3.3-30 Invalid instruction exception source (INV) Bit Configuration
The content of each bit are described below.
[bit6] DT : Data access error
This flag is set when a bus error occurs during data access to a buffer-disabled area, or a system
register is accessed in user mode.
[bit5] IF : Instruction fetch error
This flag is set when a bus error occurs during instruction fetch, and the instruction is executed.
[bit4] FPU : FPU absence error
This flag is set when an floating point type instruction is executed on a model without FPU installed.
[bit3] PI : Privilege instruction execution
This flag is set when a RETI or STILM instruction is executed in user mode.
[bit2] SPR : System-dedicated register access
This flag is set when a MOV or LD instruction is executed to the table base register (TBR), system
stack pointer (SSP), or the exception status register (ESR) in user mode.
[bit1] DS : Invalid instruction placement on delay slot
This flag is set when an instruction that cannot be placed on delay slot is executed on the delay slot.
[bit0] RI : Undefined instruction
This flag is set when an undefined instruction code is being executed.
bit0
PIFPUIF
bit6
DT SPR DS RI
Initial value
0000000
B