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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 75
FR81 Family
CHAPTER 5 PIPELINE OPERATION
5.3
5.3.3 Interlocking
Instructions that are relatively slow in loading data to the CPU may cause data hazards that cannot be
handled by register bypassing.
In the example Figure 5.3-3, data required for the ID stage of the SUB instruction must be loaded to the
CPU in the MA stage of the LD instruction, creating a data hazard that cannot be avoided by the bypass
function.
Figure 5.3-3 Example: Data Hazard that cannot be avoided by Bypassing
In cases such as this, the CPU executes the instruction correctly by pausing before the execution of
subsequent instruction. This function is called interlocking.
In the example in Figure 5.3-4, the ID stage of the SUB instruction is delayed until the data is loaded from
the MA stage of the LD instruction.
Figure 5.3-4 Example of Interlocking
5.3.4 Interlocking produced by reference to R15 after
Changing the Stack flag (S)
The general purpose register R15 is designed to function as either the system stack pointer (SSP) or user
stack pointer (USP). For this reason the FR Family CPU is designed to automatically generate an interlock
whenever a change to the stack flag (S) in the program status (PS) is followed immediately by an instruction
that references the R15. This interlock enables the CPU to reference the SSP or USP values in the order in
which they are written in the program.
Hardware design similarly generates an interlock whenever a TYPE-A format instruction immediately
follows an instruction that changes the value of Stack flag (S). For information on instruction formats, see
Section "6.2.3 Instruction Formats".
5.3.5 Structural Hazard
A structural hazard occurs if a resource conflict occurs between instructions which use the same hardware
resource. If this hazard is detected, the pipeline is interlocked to pause the processing of subsequent
instruction until the hazard is eliminated.
IF ID EX MA WB : Data read cycle to R
0
: Read cycle from R1
IF ID EX MA WBSUB R1, R2
LD @R0, R1
IF ID EX MA WB : Data read cycle to R0
: Read cycle from R1
IF ID ID MAEX WBSUB R1, R2
LD @R0, R1