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56 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 4 RESET AND "EIT" PROCESSING
4.5
3. The contents of the program status (PS) are saved to the PS save register (PSSR).
PS → PSSR
4. The contents of the program counter (PC) of the instruction next to that accepted the break interrupt are
saved to the PC save register (PCSR).
PC → PCSR
5. An instruction is fetched from the emulator debug instruction register (EIDR1), and the handler is
executed.
4.5.4 Data Access Error Interrupt
Data access error interrupts occur when a bus error occurs during data access to the buffer enabled
specified area. Data access error interrupts can be enabled/disabled using the data access error interrupt
enable bit (MPUCR:DEE). After a data access error interrupt occurs, a new data access error interrupt will
not occur until the data access error bit (DESR:DAE) is cleared.
The data access error interrupt acceptance conditions are described below.
• The data access error interrupt enable bit (MPUCR:DEE) is enabled.
• A bus error occurs during data access to the buffer enabled specified area.
The following operations are carried out if a data access error interrupt is accepted.
1. Transition to privilege mode is carried out, and the stack flag (S) is cleared.
"0" → UM "0" → S
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP PS → (SSP)
3. The contents of the program counter (PC) of the instruction which accepted the interrupt are saved to the
system stack.
SSP - 4 → SSP PC → (SSP)
4. The program counter (PC) value is updated.
(TBR + 3DC
H
) → PC
5. A new EIT event is detected.