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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 25
CHAPTER 3 PROGRAMMING MODEL
3.3
3.3.7 System Condition Code Register (SCR)
System condition code register (SCR) is a 3-bit register used to control the intermediate data of stepwise
division and step trace trap. It lies between bit10 to bit8 of the program status (PS).
Figure 3.3-8 shows the bit configuration of system condition code register (SCR).
Figure 3.3-8 System Condition Code Register (SCR) Bit Configuration
The contents of each bit are described below.
[bit10, bit9] D1, D0: Step Intermediate Data
These bits are used for intermediate data in stepwise division. This register is used to assure
resumption of division calculations when the stepwise division program is interrupted during
processing.
If changes are made to the contents of the intermediate data (D1, D0) during division processing, the
results of the division are not assured. If another processing is performed during stepwise division
processing, division can be resumed by saving/retrieving the program status (PS) in/from the system
stack.
Intermediate data (D1, D0) of stepwise division is made into a set by referencing the dividend and
divisor by executing the "DIV0S" instruction. It is cleared by executing the "DIV0U" instruction.
The initial value of intermediate data (D1, D0) of stepwise division after a CPU reset is undefined.
[bit8] T: Step Trace Trap Flag
This flag specifies whether the step trace trap operation has to be enabled or not. When the step trace
trap flag (T) is set to "1", step trace flag operation is enabled and the CPU generates an EIT event by
trap operation after each instruction execution.
Table 3.3-9 Step Trace Trap Flag (T) of System Condition Code Register
When the step trace trap flag (T) is "1", all NMI & user interrupts are disabled.
Step trace trap function uses an emulator. During a user program which uses the emulator, step trace
trap function cannot be used (the emulator cannot be used for debugging in the step trace trap
routine).
The initial value of step trace trap flag (T) after a reset is "0".
bit10 bit9 bit8
D1 D0 T
Initial value
XX0
B
flag value Meaning
T
0 Step trace trap disabled
1 Step trace trap enabled