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FR81 Family
464 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CCR
Condition Code Register (CCR).....................21, 23
CMP
CMP (Compare Immediate Data and Destination
Register) .............................................165
CMP (Compare Word Data in Source Register and
Destination Register)............................167
CMP2 (Compare Immediate Data and Destination
Register) .............................................169
Condition Code Register
ANDCCR (And Condition Code Register and
Immediate Data)..................................127
Condition Code Register (CCR)...........................23
ORCCR (Or Condition Code Register and Immediate
Data) ..................................................362
Correction
DIV2 (Correction When Remain is 0).................177
DIV3 (Correction When Remain is 0).................179
DIV4S (Correction Answer for Signed Division)
..........................................................181
CPU
Features of FR80 Family CPU ...............................2
FR80 Family CPU Register Configuration ............16
D
Data Access
Data Access .......................................................14
Data Structure
Data Structure ....................................................12
Dedicated Registers
Configuration of Dedicated Registers ...................19
Dedicated Registers ............................................19
Delay Slot
Branching Instructions and Delay Slot ..................97
Delayed Branching
Delayed branching processing..............................78
Delayed Branching Instruction
Delayed Branching Instructions ...........................97
Example of processing of delayed branching
instruction.............................................79
Specific example of Delayed Branching Instructions
............................................................98
Destination Register
ADD (Add 4bit Immediate Data to Destination
Register) .............................................105
ADD2 (Add 4bit Immediate Data to Destination
Register) .............................................109
ADDN (Add Immediate Data to Destination Register)
..........................................................113
ADDN2 (Add Immediate Data to Destination
Register) .............................................117
CMP (Compare Immediate Data and Destination
Register) .............................................165
CMP2 (Compare Immediate Data and Destination
Register).............................................169
LDI:8 (Load Immediate 8bit Data to Destination
Register).............................................300
Direct Address
Direct Address Area .............................................8
DMOV (Move Word Data from Direct Address to
Post Increment Register Indirect Address)
..........................................................187
DMOV (Move Word Data from Direct Address to
Pre Decrement Register Indirect Address)
..........................................................191
DMOV (Move Word Data from Direct Address to
Register).............................................183
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................189
DM
OV (Move Word Data from Register to Direct
Address).............................................185
DMOVB (Move Byte Data from Direct Address to
Post Increment Register Indirect Address)
..........................................................199
DMOVB (Move Byte Data from Direct Address to
Register).............................................195
DMOVB (Move Byte Data from Register to Direct
Address).............................................197
DMOVH (Move Halfword Data from Direct Address
to Register).........................................203
DMOVH (Move Halfword Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................207
DIV
DIV0S (Initial Setting Up for Signed Division)
..........................................................171
DIV0U (Initial Setting Up for Unsigned Division)
..........................................................173
DIV1 (Main Process of Division).......................175
DIV2 (Correction When Remain is 0) ................177
DIV3 (Correction When Remain is 0) ................179
DIV4S (Correction Answer for Signed Division)
..........................................................181
Division
DIV0S (Initial Setting Up for Signed Division)
..........................................................171
DIV0U (Initial Setting Up for Unsigned Division)
..........................................................173
DIV1 (Main Process of Division).......................175
DIV4S (Correction Answer for Signed Division)
..........................................................181
Signed Division................................................100
Step Division Instructions .................................100
Unsigned Division............................................101