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FR81 Family
250 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.77
7.77 FMADDs (Single Precision Floating Point Multiply and
Add)
FRk is multiplied by FRj, and FRi is added to its result and then stored in FRi.
● Assembler Format
FMADDs FRk, FRj, FRi
● Operation
FRk × FRj + FRi → FRi
● Classification
Single-precision floating point instruction, FR81 family
● Execution Cycles
4 cycles
● Instruction Format
● EIT Occurrence and Detection
An invalid instruction exception (FPU absence error), an FPU exception, or an interrupt is detected.
MSB LSB
(n+0)0000011110100101
(n+2) - FRk FRj FRi