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58 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 4 RESET AND "EIT" PROCESSING
4.6
The following operations are carried out when an INTE instruction is executed during normal operation.
1. Transition to privilege mode is carried out, the stack flag (S) is cleared, and 4 is set to the interrupt level
mask register (ILM).
"0" → UM "0" → S"4" → ILM
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP PS → (SSP)
3. The contents of the program counter (PC) of the subsequent instruction are saved to the system stack.
SSP - 4 → SSP next instruction address → (SSP)
4. The program counter (PC) value is updated by referring to the vector table.
(TBR + 3D8
H
) → PC
5. A new EIT event is detected.
The following operations are carried out when an INTE instruction is executed in the user state during
debugging.
1. Transition to privilege mode is carried out, the stack flag (S) is cleared, 4 is set to the interrupt level
mask register (ILM), and then the mode is shifted to the debug state.
"0" → UM "0" → S"4" → ILM
2. The contents of the program status (PS) are saved to the PS save register (PSSR).
PS → PSSR
3. The contents of the program counter (PC) of the subsequent instruction are saved to the PS save register
(PCSR).
PC → PCSR
4. An instruction is fetched from the emulator debug instruction register (EIDR1), and the handler is
executed.
The address saved in the system stack as program counter (PC) represents the address of the next
instruction after the "INTE" instruction.
The INTE instruction should not be used within a trap processing routine of step trace trap.
4.6.3 Step Trace Traps
Step trace traps are traps used for debugging programs. Through this, a trap can be created after the
execution of each instruction by setting the step trace trap flag (T) in the system condition code register
(SCR). The operation of the step trace trap varies between the user state during debugging and normal
operation.
A step trace trap is accepted when an instruction for which the step trace trap flag (T) is changed from "0"
to "1" is executed. A step trace trap does not occur when an instruction for which the step trace trap flag (T)
is changed from "1" to "0" is executed. However, for RETI instructions, a step trace trap does not occur
when a RETI instruction for which the step trace trap flag (T) is changed from "0" to "1"is executed.