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456 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
APPENDIX
APPENDIX C Supplemental Explanation about FPU Exception Processing
C.2 FPU Exceptions
FPU exceptions are classified into six types: five exceptions (Inexact, Underflow, Overflow, Division by
Zero, and Invalid Calculation), which are defined in IEEE754, and an exception that is generated when an
unnormalized number is input. Whether or not to generate those calculation exceptions can be specified
using the FPU control register (FCR.EEF). The result output upon the exception conditions being satisfied
varies depending on the FCR.EEF setting.
If an exception is not permitted, the result of each calculation is output so that the requested result is
obtained when calculation runs on even if an exception occurs, or so that it can be recognized from the
result that the calculation is invalid. When an exception is permitted, if the significant calculation result
cannot be obtained due to an exception factor, the calculation result is not written; otherwise, it is written.
1. Invalid calculation exception (Invalid Operation)
This exception occurs when calculation cannot be carried out properly because the specified operand is
invalid for the calculation. In concrete terms, this exception occurs when:
• SNaN has been input;
• the result is in infinite format (∞ - ∞, 0 × ∞, 0/0, ∞/∞, etc.)
• the conversion source value is not indicated in the conversion destination format using a conversion
instruction.
If this exception occurs, the following operations are carried out.
[FCR:EEF:V=1]
Writing to the floating point register or FCR:FCC is prohibited.
The FCR.CEF.V flag is set to generate an FPU exception.
[FCR:EEF:V=0]
QNaN (7FFFFFFF
H
) is stored in the floating point register for instructions other than conversion or
comparison instructions.
For the conversion instruction, ± MAX is stored in the floating point register.
For the comparison instruction, the FCR:FCC:U flag is set.
The FCR:ECF:V flag is set.
2. Division-by-Zero exception (Division by Zero)
This exception occurs when performing division by zero. If this exception occurs, the following
operations are carried out.
[FCR:EEF:Z=1]
Writing to the floating point register is prohibited.
The FCR:CEF.Z flag is set to generate this exception.
[FCR:EEF:Z=0]
The infinity is stored in the floating point register. If the sign is the same, it is set to a positive sign. If
the sign is different, it is set to a negative sign.
The FCR:ECF:Z flag is set.
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