Filter
Top Products
FR81 Family
14 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 2 MEMORY ARCHITECTURE
2.3
2.3 Word Alignment
The data type used determines restrictions on the designation of memory addresses
(word alignment).
2.3.1 Program Access
Unit of instruction length is half word (2byte) and all instructions are allocated to addresses which are
multiples of 2 (2n location).
At the time of execution of the instruction, bit0 of the program counter (PC) automatically becomes "0",
and is always at an even address. In a branched instruction, even if an odd address is generated as a result
of branch destination address calculation, the bit0 of the address will be assigned "0" and branched to an
even address.
There is no address exception in program access.
2.3.2 Data Access
There are following restrictions on addresses for data access depending upon the data type used.
Word data
Data is assigned to addresses that are multiples of 4 (4n location). The restriction of multiples of 4
on addresses is called ‘word boundary’. If the specified address is not a multiple of 4, the lower two
bits of the address are set to "00" forcibly.
Half-word data
Data is assigned to addresses that are multiples of 2 (2n locations). The restriction of multiples of 2
on addresses is called ‘half-word boundary’. If the specified address is not a multiple of 2, the lower
1 bit of the address is set to "0" forcibly.
Byte data
There is no restriction on allocation of addresses.
During word and half-word data access, condition that lower bit of an address has to be "0" is applicable
only for the result of computation of an effective address. Values still under calculation are used as they
are.