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FR81 Family
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 467
MULUH (Multiply Unsigned Halfword Data)
..........................................................352
ORH (Or Halfword Data of Source Register to Data
in Memory).........................................364
STH (Store Halfword Data in Register to Memory)
..........................................401, 403, 405
hazard
Occurrence of register hazard...............................74
Register hazards .................................................74
I
I
Timing when the interrupt enable flag (I) is requested
............................................................63
ILM
Interrupt Level Mask Register (ILM)....................22
Immediate 20bit Data
LDI:20 (Load Immediate 20bit Data to Destination
Register) .............................................296
Immediate 32 bit Data
LDI:32 (Load Immediate 32 bit Data to Destination
Register) .............................................298
Immediate 8bit Data
LDI:8 (Load Immediate 8bit Data to Destination
Register) .............................................300
Immediate Data
ADD (Add 4bit Immediate Data to Destination
Register) .............................................105
ADD2 (Add 4bit Immediate Data to Destination
Register) .............................................109
ADDN (Add Immediate Data to Destination Register)
..........................................................113
ADDN2 (Add Immediate Data to Destination
Register) .............................................117
ADDSP (Add Stack Pointer and Immediate Data)
..........................................................119
BANDH (And 4bit Immediate Data to Higher 4bit of
Byte Data in Memory)..........................137
BANDL (And 4bit Immediate Data to Lower 4bit of
Byte Data in Memory)..........................139
BEORH (Eor 4bit Immediate Data to Higher 4bit of
Byte Data in Memory)..........................145
BEORL (Eor 4bit Immediate Data to Lower 4bit of
Byte Data in Memory)..........................147
BORH (Or 4bit Immediate Data to Higher 4bit of Byte
Data in Memory) .................................149
BORL (Or 4bit Immediate Data to Lower 4bit of Byte
Data in Memory) .................................151
CMP (Compare Immediate Data and Destination
Register) .............................................165
CMP2 (Compare Immediate Data and Destination
Register) .............................................169
ORCCR (Or Condition Code Register and Immediate
Data) ..................................................362
STILM (Set Immediate Data to Interrupt Level Mask
Register).............................................408
Increment Register
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
..................................................189, 193
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................201
Indirect Address
DMOV (Move Word Data from Direct Address to
Post Increment Register Indirect Address)
..........................................................187
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................189
Instruction
“INT”Instructions...............................................57
Branching Instructions and Delay Slot..................97
Delayed Branching Instructions ...........................97
Example of branching with non-delayed branching
i
nstructions ...........................................78
Example of processing of delayed branching
instruction ............................................79
Instruction execution based on Pipeline ................70
INTE Instruction ................................................57
Non-Delayed Branching Instructions....................99
Read-Modify-Write type Instructions ...................96
Specific example of Delayed Branching Instructions
............................................................98
Step Division Instructions .................................100
Instruction Format
Instruction Formats.............................................87
Instructions Formats ...........................................85
Instruction System
Instruction System..............................................82
Instructions Notation Formats
Instructions Notation Formats..............................85
INT
“INT”Instructions...............................................57
INT (Software Interrupt)...................................271
INTE
INTE (Software Interrupt for Emulator) .............273
INTE Instruction ................................................57
Interlocking
Interlocking .......................................................75
Interlocking produced by reference to R15 and
General-purpose Registers after Changing
the Stack flag (S flag) ............................75
Interrupt
General interrupts...............................................53
INT (Software Interrupt)...................................271
INTE (Software Interrupt for Emulator) .............273
Interrupts...........................................................53