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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 455
FR81 Family
APPENDIX
APPENDIX C Supplemental Explanation about FPU Exception Processing
APPENDIX C Supplemental Explanation about FPU Exception
Processing
C.1 Conformity with IEEE754-1985 Standard
The FR81 Family CPU conforms to the IEEE754-1985 standard (hereinafter referred to as "IEEE754"),
excluding the following.
1. Overflow
IEEE754 defines that the biased (+192 for single-precision) exponent part is used as the result if overflow
occurs; however, this architecture does not provide for certain cases such as the addition of the biased
value.
2. Underflow
IEEE754 defines that the biased (-192 for single-precision) exponent part is used as the result if
underflow occurs; however, this architecture does not provide for certain cases such as the reduction of
the biased value.
When the result is an unnormalized number, the result is flushed to zero.
3. Unnormalized number
IEEE754 defines an unnormalized number to prevent the result from being flushed rapidly to zero;
however, the unnormalized number is not supported in this architecture. If an unnormalized number is
input when the unnormalized number input exception is prohibited, its numeric value is assumed to be
zero for calculation purposes. This is also applied when the calculation result is an unnormalized number;
therefore, the result is set to zero.
4. QNaN
The QNaN output pattern is fixed to 7FFFFFFF
H
, excluding the move, sign inversion, and absolute value
instructions.
5. Unsupported instructions
This architecture does not support the following instructions.
• Remainder
• Integer rounding (Round Floating-Point Number to Integer Value)
• Conversion between binary and decimal numbers
6. Floating point calculation exception
This exception occurs when the sufficient calculation result is not obtained for IEEE754. This
architecture provides six exceptions in total: five exceptions (Inexact, Underflow, Overflow, Division by
Zero, and Invalid Calculation), which are defined in IEEE754, as well as one exception (unnormalized
number input).
In IEEE754, if a floating point calculation exception occurs, the defined operation is carried out to
generate a trap. In this architecture, it is provided as an exception; therefore, no data is written to the
destination when a floating point calculation exception occurs.