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5700A/5720A Series II Calibrator
Service Manual
2-42
2-80. Inguard Clock Circuit
This circuit uses 8 MHz crystal Y52 and step-down transformer T51 to generate a low-
level (200 mV p-p) 8 MHz clock used by other guarded assemblies throughout the
calibrator. Transformer (T51) has a center-tapped secondary, and provides CLK COM,
CLK and CLK*. The CLK and CLK* sine-wave signals are sent to certain analog
assemblies where they are converted into square wave clock signals for timing purposes.
2-81. Inguard Watchdog Timer
The watchdog timer circuit uses a 74HC4020 (U59) and part of Programmable Logic
Device (PLD) U58. The microcontroller (U56) generates a 19.2 kHz square wave
(SCLK) on pin 11. The frequency of this clock is the same as the baud rate of the serial
interface. Once the clock frequency is initialized, it runs without software supervision.
This clock drives U59, which divides by 16384 to obtain a logic low interval of 427 ms
followed by a logic high interval of 427 ms. The output of the U59, POPIN, goes to the
PLD, which asserts POP to the analog hardware and NMIPOP* to the processor if U59 is
not reset every 427 ms. The PLD also asserts POP on power-up and on any hardware
reset. In order to prevent POP and NMIPOP*, the watchdog counter must be reset by
reading or writing any analog hardware, or by toggling the POPCLRL line. The
POPCLRL line is also used to disable the watchdog by going low.
2-82. Power-Up and Reset Circuitry
This circuit consists of U60, SW51, C55, C56, R52, and Z51. The line monitor chip
(U60) detects three events: the power supply falling below 4.5V, reset being initiated by
closure of momentary contact switch SW51, or BREAK being asserted from the break
detection circuitry. If any of these conditions occurs, U60 resets the board for 130 ms.
Pin 5 of U60 is an open-collector output, pulled high by pin 12 of Z51.
2-83. Break Detection
The break-detect circuit acts as a serial communications break detector enabling the CPU
assembly (A20) to reset U56 and U58 via the power-up and reset circuitry. This break-
detect circuit uses a 74HC4020 binary counter (U63) and an inverter U51C. The
microcontroller (U56) outputs the 1.2288 MHz ECLK clock on pin 64. This signal
clocks U63, which in turn divides the signal by 16,384 to produce successive logic low
and high intervals (each of 6.67 ms) at the BREAK output (U63, pin 3). Under normal
conditions the RCV (receive) line is high to hold U63 clear. The main 68HC000 CPU
can force a reset of the Guard Crossing over the fiber-optic link by holding RCV low for
more than 6.67 ms, which causes BREAK to go high. BREAK, inverted by U51C, is
used by the reset circuitry to force a Guard Crossing reset via RESET*.
2-84. Fiber-Optic Link to CPU
Guarded digital and analog circuits are isolated from the unguarded CPU assembly
(A20) by a fiber-optic link that asynchronously transmits serial data. On the transmit
side, the microcontroller transmit output (XMT) controls a 75451 (U57) which drives
fiber-optic transmitter J72 mounted on the Analog Motherboard. Receive signal RCV
comes from fiber-optic receiver J71 also mounted on the Analog Motherboard. The
receiver converts the light signal to TTL levels that become the RCV signal at the
microcontroller. A fiber-optic cable links the fiber-optic transmitter on the Analog
Motherboard to the fiber-optic receiver on the Digital Motherboard. Another fiber-optic
cable links the other receiver/transmitter pair on the motherboards.