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5700A/5720A Series II Calibrator
Service Manual
2-24
2-33. Watchdog Timer
The watchdog timer circuitry uses a 74HC4020 binary counter (U11) to divide the 450
Hz from the clock generation circuit to produce interrupt DOGINTH, signifying that the
system may be locked up. This interrupt is generated 1.14 seconds after the last
DOGCLR2 signal from interrupt controller U10. Therefore, DOGCLR2 must occur more
often then every 1.14 seconds to clear U11 and prevent the watchdog interrupt.
Generation of DOGCLR2 is under software control. The watchdog timer can be disabled
by cutting jumper E1.
2-34. Address Decoding and DTACK (Data Acknowledge)
Two Programmable Logic Devices (PLDs) accomplish address decoding and DTACK
(data acknowledge) generation. ICs U5 and U6 provide chip selects and generate
acknowledgment signals for those devices without DTACK lines. IC U5 receives
DTACK signals from the asynchronous devices and ORs these signals together to form
DTACK*. Table 2-4 is the memory map for the system. It shows the chip select, address
range, and notes whether AS* (address strobe) or LDS* (lower data strobe) is required.
Table 2-4. CPU Memory Map
Chip Select Read/Write Address Range AS* or LDS* Required?
PROM0CS* R 0 to 3FFFF no
PROM1CS* R 40000 to 7FFFF no
PROM2CS* R 80000 to BFFFF no
RAM0CS* 600000 to 60FFFF no
RAM1CS* 610000 to 61FFFF no
RAM2CS* 620000 to 623FFF no
NVMCS* R/W C00000 to CFFFFF no
MISCCS* R/W D00000 to DFFFFF no
RPSEL* R/W D00000 to D01FFF LDS*
RPDUARTCS* R/W D00000 to D0001F LDS*
RPIEEECS* R/W D00020 to D0002F LDS*
Y52XXRD* R D00030 to D00031 LDS*
Y5205WR* W D00032 to D00033 LDS*
Y5220WR* W D00034 to D00035 LDS*
FRNTPNLCS* R/W D02000 to D03FFF AS*
OTDCS* R/W D02000 to D027FF AS*
DMDCS* R/W D02800 to D02FFF AS*
ENCODERCSR R D03000 to D033FF AS*
ENCODERRESETW W D03000 to D033FF AS*
LED_OUTPUT_ R R D03400 to D037FF AS
LED_LATCH_EN R/W D03400 to D037FF AS*
KEYBOARDCS R/W D03800 to D038FF AS*
GCDRTCS* D04000 to D05FFF LDS*
XDUARTCS* R/W D06000 to D07FFF LDS*
RDINT* W D08000 to D09FFF AS*
DOGCLR D08000 to D09FFF even only, AS*
ADCLKCS* E00000 to EFFFFF AS*