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Theory of Operation
Analog Section Detailed Circuit Description
2
2-43
2-85. Interface to Guarded Digital Bus
The interface to the guarded digital bus consists of a 74HCT245 (U55), a 74HCT244
(U52), two 74HC137s (U53 and U54), inverters U51B and U51D, resistor packs Z52,
Z53, and Z54, and the POP line from U58. U52A and U52B buffer various control and
address lines. Resistors from Z52 pull the lines of U52A to desired inactive states when
BUSEN* is at a logic high, disabling the bus. U55 is a bi-directional data bus buffer
(D0-D7). Resistor packs Z53 and Z54 match the lines of the buffered data bus, reducing
reflected noise. ICs U53, U54, and U51D perform a 4-to-16 decode of address lines A3-
A6, generating 16 chip-select lines (CS0*-CS15*) on the guarded digital bus. These 16
signals select the various assemblies on the Analog Motherboard. U51B buffers and
inverts the INT interrupt signal from the DAC assembly. The POP signal from U58 is a
reset line sent to the analog assemblies.
2-86. Inguard CPU Interrupts
The Inguard CPU microprocessor handles many different interrupts. These are listed in
Table 2-12 in order of priority with the highest priority interrupts first.
Table 2-12. Inguard CPU Interrupts
Vector
MSB LSB
Interrupt Description
FFFE FFFF *RES Power Up Reset
FFEE FFEF TRAP Address error or op code error
FFFC FFFD !NMI Non maskable interrupt (NMIPOPL)
FFFA FFFB SWI UNUSED
FFF8 FFF9 !IRQ1 !IRQ1,ISF (A/DINTL)
FFF6 FFF7 ICI Timer 1 input capture (unused)
FFF4 FFF5 0CI Timer 1 output compare 1,2 (unused)
FFF2 FFF3 TOI Timer 1 overflow (unused)
FFEC FFED CMI Timer 2 counter match
FFEA FFEB !IRQ2 UNUSED
FFF0 FFF1 SIO RDRF + ORFE + TDRE + PER
RDRF = Receive Data Register Full
ORFE = Overrun Framing Error
TDRE = TRANSMIT DATA REGISTER EMPTY
PER = Parity Error
2-87. Switch Matrix Assembly (A8)
Refer to Figure 2-7 for a simplified schematic of the Switch Matrix assembly (A8). The
Switch Matrix assembly does the following tasks:
• Coordinates the flow of signals from each analog assembly (excepting the Wideband
AC Module (Option -03)) to the calibrator’s binding posts. This communication
determines the calibrator’s range.
• Coordinates the connection of various analog and digital common lines during
operate, standby, and calibration modes.
• Controls such binding post functions as operate/standby, internal/external sense, and
internal/external guard.
• Provides an internal cal zero amplifier used in the calibration of offsets for all dcv
ranges (except the 1100V range).