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5700A/5720A Series II Calibrator
Service Manual
2-64
2-102. DAC Assembly Digital Control
The digital control circuit is located on sheet 6 of the DAC schematic. The 82C55
Programmable Peripheral Interface IC (U31) is the heart of this circuit.
This IC, which is under software control via the guarded digital bus, has three ports that
provide 24 static lines. Port A (PA0-PA7) is configured as a read-only port register. It
passes the adc readings from the ADC IC (U25) to the guarded digital bus.
PB0-PB4 of port B control relays K1-K4 and K6-K8 via relay drivers U33 and U34. PB0
is also control line DAC OUT SEL used to turn on FET Q25, via FET Q26, and connect
RCOM to SCOM during calibrator operation in the ac function.
PC7 of port C, buffered by U8A, provides the enable for these relay drivers. Relay driver
U33 controls latching relays K7 and K8. Outputs from U33 are also used by Relay driver
U34 to control latching relays K1-K6. PB5-PB7 are decoded by U32 to create six control
lines. These control lines are used to select one input to the adc amplifier -input. K5SEL
is an input to the relay drivers to control latching relay K5. The remaining five control
lines are used by comparators in U35 and U36. These comparators provide the proper
level shifting to create control lines BSRF6 SEL, BSRF13 SEL, REF6 SEL, REF13 SEL,
and ADC COM SEL. These control lines are used to control FETs on the DAC Buffered
Reference SIP assembly (A11A2).
PC0 of port C is buffered by U8 (B and C) and routed through opto-isolator U37 to
create RANGE SELECT, which sets the DAC to the 11V or 22V range. PC1 is used in
the duty cycle control circuit to shut off the 8 MHz clock via buffer U8F and the first
channel via OR gate U9D. This is done during calibrator operation in the resistance
function. PC2 controls a FET in U23 for use in self-diagnostics. PC3 and PC4 are level-
shifted by comparators in U36 before they are used to control FETs in U23. PC5 of port
C is connected to a comparator in U36. This comparator provides the proper level
shifting to create control line ADCAMP OUT SEL to control a FET in U23. PC6 is
control line ADC TRIGGER which triggers the adc (analog-to-digital converter) IC U25.
A0, A1, and CS*, from the guarded digital bus, are used by OR gates in U9 (B and C) to
create control line ADC READ for use by the adc IC U25.
2-103. DAC Assembly Reference Circuitry
The reference circuitry is on the reference hybrid, located on the HR5 assembly. The
HR5 assembly contains a ceramic substrate reference hybrid bonded to a resistor
network.
All components on this assembly are surface mount devices, except U6 and U7. The
resistors are screened with a thick film paste. Associated resistors, capacitors, and zener
diodes are mounted on the main board to supply this hybrid with the appropriate power
and ground returns.
As previously explained, the amplitudes of the pulse width modulated signals for the
first and second channel are assumed to be fixed. Any change in amplitude shows up as
an error on the output of the DAC. Since the reference is used to determine the
amplitude, it must be very stable and generate little noise.
The 13V reference contains two cascaded 6.5V temperature compensated
transistor/zener diode pairs called ref amps (U6 and U7). The excellent temperature
characteristics of the ref amps are obtained by biasing the collector current on their
transistors with a value such that the TC (temperature coefficient) of its base-emitter
junction cancels the TC of the zener diode. Since the base-emitter junction and the zener
diode are in series, the result is a near zero TC.
Correct bias currents are achieved with a thin-film resistor network in a surface-mount
package mounted on the hybrid.