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5700A/5720A Series II Calibrator
Service Manual
2-66
The 3V source is created from the 13V reference. The 13V reference is buffered by op
amp U1B, configured as a voltage follower. The output from U1B is divided down to 3V
by a 100 kΩ and 30 kΩ resistor in the HR5 assembly, creating 3V.
This 3V is again buffered by op amp U11, configured as a voltage follower, to create the
3V, which is switched by FETs Q30 and Q32. CH2 FILTER INPUT uses three resistors
on the HR5 assembly to resistively divide its 3V amplitude by an additional factor of
approximately 3800.
The first channel signal is buffered by U8 (G and H) and run through opto-isolator U13,
to become CH1 FLOATING. Since the first channel is much more critical than the
second, CH1 FLOATING is clocked into a flip flop (U14) to ensure an accurate
waveform.
To clock in this waveform, the low-level 8 MHz clock (CLK and CLK*) from the
Regulator/Guard Crossing assembly (A17) is isolated by transformer T1 and amplified
to a TTL level by comparator U10. This generates the clock inputs for U14. The output
Q1 (pin 5) from U14 creates CH1 SERIES A, which switches Q7. The output Q1* (pin
6) is inverted by Q35, creating CH1 SHUNT, which switches Q6. The output Q1*, which
is a TTL level, is also amplified by components Q33, Q34, VR11, VR12, and R44-R46,
so it switches from 0 to 18V, creating CH1 SERIES B, which switches Q4 and Q5.
The watchdog timer sets the first channel filter input to 0V if a failure occurs on the 8
MHz clock. This circuit uses a monostable multivibrator (one shot) U15, C63, and R48.
The 8 MHz clock is divided to 4 MHz by U14. This 4 MHz clock is connected to U15
and discharges C63 to ground. If the 4 MHz clock stops, C63 charges up, causing the Q1
output of U15 to go low. This logic low on Q1 is connected to the preset pin of U14
(PRI), which causes its Q1 output high and its Q1* output low. This condition turns on
the shunt switch and turns off the series switch, which forces the filter input to be
REFCOM.
2-105. DAC Filter Circuit
The dac filter circuit is located on the DAC Filter SIP (A11A1) assembly. The dominant
pole of the filter is near 10 Hz. This gives 120 dB of rejection at 190 Hz.
The +30FR1 supply and 15V zener diode, VR1, create the 15V supply (15V) for the op
amps in the filter circuit. 15V is also connected to the main DAC board, where it is used
with R111 as a pull up for the RANGE SELECT control line.
2-106. DAC Output Stage
The output stage of the DAC assembly consists of the DC Amplifier Hybrid assembly
(HR6) and the output buffer circuitry. Like the Reference Hybrid, the DC Amplifier
Hybrid is constructed of surface-mount components (except precision op amp U2), on a
ceramic substrate hybrid, bonded to a resistor network.
It is temperature-controlled by a heater control circuit in the same manner as explained
on the Reference Hybrid. Transistor Q3 provides proper power to the heater resistor.
The DC Amplifier Hybrid consists of a precision op amp U2, with a bootstrapped power
supply (Q1, Q2, R1-R4, VR1-VR2). The op amp has low noise and low offset. It is
bootstrapped to improve the common-mode rejection in its noninverting configuration.
The DC Amplifier assembly interfaces with the output buffer (U5) to create the output
stage. Control line RANGE SELECT configures this output stage for unity gain for the
11V range or a gain of 2 for the 22V range. In the 11V range, Q15 is turned off, which
gives U5 unity gain, and Q20 is on, which gives the DC Amplifier unity gain.