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5700A/5720A Series II Calibrator
Service Manual
2-132
2-207. Clock Regeneration Circuit
In order to minimize EMI (electro-magnetic interference) inside the Calibrator chassis,
the rear panel accepts a low-level (~200 mV p-p sinewave) 3.68 MHz clock from the
CPU assembly and conditions it to proper TTL clock levels.
This is done by a differential amplifier, U18, which amplifies the incoming signals
3.6864MHZCLK and 3.6864MHZCLK*. The output of U18 is a TTL level 3.68 MHz
clock called RP3.68MHZ that is buffered by PLD U8 creating RPCLK for use by
DUART (dual universal asynchronous receiver/transmitter) U5, and IEEE interface IC
U2.
2-208. IEEE-488 (GPIB) Interface
The IEEE-488 (GPIB) interface circuit provides the interface between the IEEE-488
connector (J1) and the calibrator processor on the CPU (A20) assembly. The circuitry
uses a TMS9914 (U2) General Purpose Interface Bus (GPIB) adapter to meet the
requirements for talker/listener operation on the IEEE-488 bus. This circuit translates
asynchronous 8 bit data and control information, under control of an external controller,
and converts this information to an acceptable format for the CPU. responds.
The TMS9914 has internal circuitry which handshakes in the proper GPIB protocol and
stores data in an internal buffer. This IC also has the capability of interrupting the CPU.
The CPU can then handle the interrupt through its own handler routine. The data lines
between U2 and J1 are buffered by a 75160A (U3) data buffer, and the command lines
are buffered by a 75162A (U4) command buffer. J1 is a standard IEEE-488 connector.
The shell of this connector is tied to chassis ground for EMI/RFI shielding.
2-209. RS-232C Interface
The RS-232C interface circuit uses a 68C681 DUART (U5), a 1488 line driver (U6), and
a 1489 line receiver (U7).
The DUART does the parallel to serial data conversion and provides two channels of
serial RS-232C communication.
The first channel is available to RS-232C connector J2 to meet serial interface needs
between the Calibrator and the external world. The transmit line (*TXDA) is driven by
U6D to TX of J2, pin 2. The receive line RX goes from J2, pin 3 through receiver U7C
to the receive line *RXDA of the DUART.
The second channel is connected to the 5725A Amplifier interconnect connector (J7) to
provide the 5725A digital control interface to the CPU assembly. Transmit line *TXDB
is driven by U6B to B-SCT of J7, pin 18. Receive line B-SCR from J7, pin 17 goes
through receiver U7B to the receive line *RCVB of the DUART. These lines are also
connected to J10, pins 2 and 3, for internal software testing.
The DUART (U5) also has six input lines, four of which are used to monitor CTSA*, B-
CINT*, CAL SWA*, and CAL SWB*. The CTS (clear to send) line from J2, pin 5 goes
through receiver U7A becoming CTSA*. Line CAL SWA* comes from the rear panel
CALIBRATION switch.
The B-CINT* input (5725A cable interlock) is a logic signal used to let the Calibrator
know that the interface cable to the 5725A Amplifier is connected and the 5725A is
energized.
The DUART (U5) generates four output lines. The first, RTSA*, is driven by U6C to the
RTS (ready to send) pin 4 of J2. The remaining three are used in the auxiliary amplifier
interface logic circuit.