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PREFACE
The Inte1386 SX processor (16-bit data bus) - The Intel386 DX processor adapted for
mid-range personal computers, which
are,
sensitive to the higher system cost of a 32-bit
bus. Related documentation includes:
•
386™
SX
Microprocessor
Data Sheet, Order Number 240187
•
386™
SX
Microprocessor
Hardware
Reference Manual, Order Number 240332
The
376
embedded processor (16-bit data bus) - A reduced form of the Intel386 pro-
cessor, optimized for embedded applications. Related documentation includes:
•
376™
Microprocessor
Data
Sheet, Order Number 240182
•
376™
Embedded
Processor
Programmer's
Reference Manual, Order Number
240314
ORGANIZATION OF THIS MANUAL.
The information in this manual
is
divided into
12
chapters and three appendices. The
material begins with a description of the Inte1386 DX microprocessor and continues with
discussions of hardware design information needed to implement Intel386 DX micropro-
cessor system designs.
• Chapter
1,
"System Overview." This chapter provides an overview of the Inte1386 DX
microprocessor and its supporting devices.
• Chapter
2,
"Internal Architecture." This chapter describes the internal architecture
of the Intel386 DX microprocessor.
• Chapter
3,
"Local Bus Interface." This chapter discusses the Inte1386 DX micropro-
cessor local bus interface. This chapter includes Inte1386 DX microprocessor signal
descriptions, memory and I/O organization, and local bus interface guidelines.
• Chapter
4,
"Performance Considerations." This chapter explores the factors that
affect the performance of an Inte1386 DX microprocessor system.
• Chapter
5,
"Coprocessor Hardware Int,erface." This chapter describes the interface
between the Inte1386 DX microprocessor and the
Intel387™
Numeric Coprocessors.
This coprocessor expands the floating-point numerical processing capabilities of the
Inte1386 DX microprocessor.
• Chapter
6,
"Memory Interfacing." This chapter discusses techniques for designing
memory subsystems
for
the Intel386 DX microprocessor.
• Chapter
7,
"Cache Subsystems." This chapter describes cache memory subsystems,
which provide higher performance at lower relative cost.
e
• Chapter
8,
"I/O Interfacing." This chapter discusses techniques for connecting I/O
devices to an Inte1386
DX
microprocessor system.
, ,
• Chapter
9,
"MULTIBUS I and Intel386 DX Microprocessor." This chapter describes
the interface between an Intel386 DX microprocessor system and the Intel
MULTIBUS I multi-master system bus.
• Chapter
10,
"MULTIBUS II and Intel386 DX Microprocessor." This chapter
describes the interface between an Intel386 DX microprocessor system and the Intel
MULTIBUS II multi-master system bus. '
iv