co
Cu
i386
m
DX
CPU
BYTE ENABLES
AOIA1
LOGIC
hi
A
...
ADDRESS
LATCH
DATA
~
1386
DX
CPU
DATA
,)I
TRANSCEIVER
...
80386STATUS
,..
SO#/S1#
LOGIC
,
WAIT-STATE
GENERATOR
J
!-
~
~
L--.-
82288
BUS
CONTROLLER
82289
BUS
ARBITER
....
MULTIBUS ADDRESS
V
.
~
MULTIBUS
DATA>
.
Figure 9-1. Intel386™
OX
Microprocessor/MULTIBUS I Interface
MULTIBUS I
231732i9-1
l
35:
c:
@)
!:j
m
c:
en
l>
z
c
a
CD
~.
Q)
~
35:
(;
::D
o
"'C
::D
o
o
m
en
en
o
::D