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MEMORY INTERFACING
6.3.3.5 DATA BUS TIMINGS
The
next timings
to
consider are
the
data
path
delays. These calculations include
data
buffers.
T
RAe
:
Read
data
access from RAS
= (6 x CLK2) - PLD RegOut Max
(RAS#)
- Intel386
DX
microprocessor
Data
Setup Min (T21) - Xcvr Prop Max
150 -
12
-
11
- 7
120 nanoseconds
T
CAS
:
Read
data
access from
CAS#
= (4 x CLK2) - PLD RegOut Max
(CAS#)
- (2 x Or-gate Prop Max) - Intel386
DX
microprocessor
Data
Setup Min - Xcvr Prop Max
=
100
- 6 - 12 -
11
- 7
=
64
nanoseconds
T
OFF
: Min
output
data hold time from
CAS#.
This is done to assure that
the
Intel386
DX
microprocessor
Data
Hold Time (T22) will
be
met
For
the
inactive
CAS#
edge:
= PLD RegOut Min
(CAS#)
+ (2 x Or-gate Prop Min) + Xcvr Prop Min - Intel386
DX
microprocessor
Read
Data
hold time (T22)
=
1.5
+ 6 +
2.5
- 6
= 4.0 nanoseconds
Therefore T
OFF
can
be
0
and
the
read
data hold time will still
be
met
For
the
inactive
DEN#
edge:
= PLD
RegOut
Min
(ALE#)
+
Or~gate
Prop Min + Xcvr Disable Min
1.5
+ 3 + 2
6.5
nanoseconds Which meets
the
Intel386
DX
Microprocessor
read
data hold
time (T22)
of
6 nanoseconds at
20
MHz.
For
write cycles the maximum Intel386
DX
microprocessor write data valid delay is 38
nanoseconds measured from
the
start
of
clock phase two.
CAS#
is
delayed two CLK2
periods till
the
start
of
the
next clock phase two
to
assure
the
data will
be
valid.
6-22