Filter
Top Products
LOCAL BUS INTERFACE
An NMI request automatically causes the Inte1386 DX microprocessor to execute the
service routine corresponding to location 2 in the IDT. The Intel386
DX
microprocessor
will
not service subsequent NMI requests until the current request has been serviced.
The Inte1386 DX microprocessor disables INTR requests (although these can
be
reen-
abled in the service routine) in Real Mode. In
Protected Mode, the disabling of INTR
requests depends on the gate in
IDT
location
2.
3.4.2 Maskable Interrupt (INTR)
The INTR input of the
Inte1386
DX microprocessor allows external devices to interrupt
Inte1386
DX
microprocessor program execution. To ensure recognition by the
Intel386 DX microprocessor, the INTR input must be held high until the Inte1386
DX
microprocessor acknowledges the interrupt
by
performing the interrupt acknowledge
sequence. The INTR input
is
sampled at the beginning of every instruction; it must be
high at least eight CLK2periods prior to the instruction to guarantee recognition
as
a
valid interrupt. This requirement reduces the possibility of false inputs from voltage
glitches. In addition, maskable interrupts must enabled in software for. interrupt recog-
nition. The INTR input
may
be asynchronous to
CLK2.
The INTR signal
is
usually supplied
by
the 8259A Programmable Interrupt Controller,
which in
tum
is
connected to devices that require interrupt servicing. The
8259A,
which
is
controlled
by
commands from the Intel386 DX microprocessor (the 8259A appears as
a set of
I/O ports), accepts interrupt requests from devices connected to the 8259A,
determines the priority for transmitting the requests to the Intel386 DX microprocessor,
activates the INTR input, and supplies the appropriate service routine vector when
requested.
An INTR request· causes the Intel386 DX microprocessor to execute two back-to-back
interrupt acknowledge bus cycles, as described earlier in
Section 3.1.7. .
3.4.3 Interrupt Latency
The time that elapses before an interrupt request
is
serviced (interrupt latency) varies
according to several factors. This delay must be taken into account
by
the interrupt
source. Any of the following factors can affect interrupt latency:
•
If
interrupts are masked, an
INTR
request will not be recognized until interrupts are
reenabled.
•
If
an NMI
is
currently being serviced, an incoming NMI request
will
not be recog-
nized until the
Inte1386
DX microprocessor encounters the
IRET
instruction.
•
If
the Intel386 DX microprocessor
is
currently executing an instruction, the instruc-
tion must be completed.
An
interrupt request
is
recognized
oI).ly
on an instruction
boundary. (However, Repeat
String instructions can be interrupted after each
iteration. )
3-29