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MULTIBUS I AND Intel386
DX
MICROPROCESSOR
9.7 DUAL-PORT
RAM
WITH MULTIBUS I
A dual-port RAM
is
a memory subsystem that can be accessed
by
both the Inte1386
DX
microprocessor, through its local bus, and other processing subsystems, through the
MULTIBUS I system bus. Dual-port RAM offers some of the advantages of both local
resources and system resources.
It
is
an effective solution when using only local memory
or only system memory would decrease system cost and/or performance significantly.
The Inte1386
DX
microprocessor accesses dual-port RAM through its high-speed local
bus, leaving MULTIBUS I free for other system operations.
Other processing sub-
systems can pass data to and from the Intel386 DX microprocessor through the dual-
port RAM using MULTIBUS
I.
If
necessary, dual-port RAM can be mapped to reserve address ranges for the exclusive
use of the InteI386 DX microprocessor. The Intel386 DX microprocessor and the other
processing subsystems need not use the same address mapping for dual-port RAM.
The disadvantage of dual-port RAM
is
that its design
is
more complex than that of
either local or system memory. Dual-port RAM requires arbitration logic to ensure that
only one of the two buses gains access at one time.
9.7.1 Avoiding Deadlock with Dual-Port
RAM
The MULTIBUS-LOCK# signal and the
Inte1386
DX microprocessor
LOCK#
signal
mediate contention when both the Intel386 DX microprocessor and a MULTIBUS I
device attempt to access dual-port RAM. However, locked cycles to dual-port RAM can
potentially result in deadlock. Deadlock arises when the Intel386
DX
microprocessor
performs locked cycles to ensure back-to-back accesses to dual-port RAM and MULTI-
BUS
I.
Suppose the Intel386
DX
microprocessor locks an access to dual-port RAM followed
by
a MULTIBUS access, to ensure that the accesses are performed back-to-back. (This
could happen only in protected mode during interrupt processing when the IDT
is
in
the
dual-port RAM and the target descriptor
is
in MULTIBUS RAM.)
At
the same time the
InteI386
DX
microprocessor performs the first locked cycle, another device gains control
of MULTIBUS I for the purpose of accessing dual-port RAM. The Inte1386 DX micro-
processor cannot gain control of MULTIBUS I to complete the locked operation, and
the other device cannot relinquish control of MUL TIBUS I because it cannot complete
its access to dual-port RAM. Each device therefore enters an interminable wait state.
Two approaches can be used to avoid deadlock:
• Requiring software to be free of locked accesses to dual-port RAM.
• Designing hardware to negate the
LOCK#
signal for transfers between dual-port
RAM and MULTIBUS
I.
If
this approach
is
used, software writers must be informed
that such transfers
will
not be locked even though software dictates locked cycles.
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