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CACHE SUBSYSTEMS
of the state
of
A20, the memory subsystem
will
always see it inactive.
In
Protected Mode,
the true state
of
A20
is
forwarded to the system. Beginning with the
82385
(B) step, 6 ns
of time will be available from the Intel386
DX
microprocessor A20 valid specification
to
the 82385 A20 setup specification. This allows a logic gate (such
as
a 74AS08) to reside
between the Intel386
DX
microprocessor and the 82385 for the A20 line. The A20
address line can be manipulated between the Intel386
DX
microprocessor and the 82385
in order to handle any possible coherency issues.
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