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MULTIBUS II AND Intel386 DX MICROPROCESSOR
10.2.1 iPSe Interface
Each bus agent must provide a means of transferring data between its Intel386 DX
microprocessor, its interconnect registers, and the iPSB bus. The location of bus inter-
face logic to meet this requirement
is
shown in Figure
10-2.
A full-featured subsystem
may also include provisions for the message passing protocols used
by
the iPSB bus.
The
iPSB interface may be conveniently implemented
by
a Bus Arbiter/Controller
(BAC), a Message Interrupt Controller (MIC), and miscellaneous logic. The BAC coor-
dinates direct interaction with the other devices on the
iPSB bus, while the MIC works
through the BAC to send and receive interrupt messages.
Other logic
is
needed for
address decoding, parity checking, and control signal generation.
The BAC and MIC are implemented in
Intel
gate arrays. In addition, Intel has devel-
oped an advanced
CMOS device, the Message Passing Coprocessor (MPC), that inte-
grates the functions of the BAC and the MIC plus parity checking and full message
passing (solicited and unsolicited), all in one package. Detailed information on the
MPC
82389
is
available in the
Microprocessor
arid
Peripheral
Handbook, Order Number
230843.
10.2.1.1 BAC SIGNALS
The BAC provides arbitration and system control logic for the arbitration, transfer, and
exception cycles defined
by
the MULTIBUS II architecture. Through the BAC, the bus
agent functions
as
either a requestor or a replier in a transfer cycle. In all cases, the
device requiring
iPSB bus access (either the Intel386 DX microprocessor or the MIC)
is
completely isolated from the
iPSB;
the BAC provides all direct interaction.
LOCAL
INTERCONNECT
MESSAGES
ALL
EXTERNAL
REFERENCES
BUS INTERFACE
FUNCTIONAL PATHS
LOCALMEM
OR I/O ACCESS
BUS
INTERFACE
LOGIC
INCOMING
INTERCONNECT
REFERENCE
IPSBBUS
INTERCONN£CT
REFERENCES
INCOMING
MESSAGE
Figure 10-2. iPSB Bus Interface,
10-4
INTERCONNECT
SPACE
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