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COPROCESSOR HARDWARE INTERFACE
• The Intel387
DX
math coprocessor
READY#,
ADS#,
and
W/R#
inputs are con-
nected. to the corresponding pins on the Intel386
DX
microprocessor.
READY
# and
ADS#
are used
by
the Inte1387
DX
math coprocessor to track bus activity and deter-
mine when
W/R#,
NPS1#, NPS2, and Status Enable (STEN) can be sampled.
• Status Enable (STEN) serves
as
a chip select for the Inte1387
DX
math coprocessor.
This pin
is
high to enable the Intel387
DX
math coprocessor, and may be driven
low
to float all Inte1387
DX
math coprocessor outputs. STEN may
be
used to do onboard
testing (using the overdrive method). STEN may also be used to activate one
Inte1387
DX
math coprocessor at a time, in systems with multiple Inte1387
DX
math
coprocessors.
If
not needed, STEN should be pulled high.
• Ready Out
(READYO#)
can
be
used to acknowledge Intel387
DX
math coprocessor
bus cycles. The Intel387
DX
math coprocessor activates
READYO#
at such a time
that write cycles are terminated after two clocks and read cycles are terminated after
three clocks.
READYO#
can be connected to the Inte1386
DX
microprocessor
READY
# input through logic that ORs
READY
# signals from other devices. Alter-
natively,
READYO#
can .be left disconnected, and external logic can be used to
acknowledge Inte1387
DX
math coprocessor bus cycles.
5.1.2 Intel387
OX
Math Coprocessor
Bus
Cycles
When the Inte1386
DX
microprocessor encounters a coprocessor instruction, it automat-
ically generates one or more
I/O cycles to addresses 800000F8H and 800000FCH. The
Intel386
DX
microprocessor
will
perform all necessary bus cycles to memory and trans-
fer data to and from the Inte1387
DX
math coprocessor. All Intel387
DX
math copro-
cessor transfers are
32
bits wide.
If
the memory subsystem
is
only
16
bits wide, the
Intel386
OX microprocessor automatically performs the necessary conversion before
transferring data to or from the Intel387
DX
math coprocessor. Since the Intel387
DX
math coprocessor
is
a 32-bit device, BS16# must not be asserted during Intel387
DX
math coprocessor communication cycles.
Read
cycles (transfers from the Intel387
DX
math coprocessor to the Intel386
DX
microprocessor) require at least one wait state, whereas write cycles to the Intel387
DX
math coprocessor require no wait states. This requirement
is
automatically reflected in
the state of the
READYO#
output of the Intel387
DX
math coprocessor, which can be
used to generate the necessary wait state.
5.1.3 Intel387
OX
Math Coprocessor Clock Input
The Intel387
DX
math coprocessor can be operated in two modes.
In
either mode, the
CLK2 signal must be connected to the 386CLK2 input of the Intel387
DX
math copro-
cessor because the interface to the Intel386
DX
microprocessor
is
always synchronous.
The state of the Intel387
DX
math coprocessor CKM input determines its mode:
•
In
synchronous mode, CKM
is
high and the 387CLK2 input
is
not connected. The
Intel387
DX
math coprocessor operates from the CLK2 signal. Operation
of
the
Intel387
DX
math coprocessor
is
fully synchronous with that of the Intel386
DX
microprocessor.
5-4